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1 ? fn6311.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) and xdcp are registered trademarks of intersil americas inc. copyright intersil americas inc. 2006, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. isl22419 single digitally c ontrolled potentiometer (xdcp?) low noise, low power, spi ? bus, 128 taps, wiper only the isl22419 integrates a si ngle digitally controlled potentiometer (dcp) and non-volatile memory on a monolithic cmos integrated circuit. the digitally controlled potentio meter is implemented with a combination of resistor el ements and cmos switches. the position of the wiper is controll ed by the user through the spi serial interface. the potentiometer has an associated volatile wiper register (wr) and a non-volatile initial value register (ivr) that can be directly written to and read by the user. the contents of the wr controls the position of the wiper. at power-up the device recalls the content of the dcp?s ivr to the wr. the dcp can be used as a voltage divider in a wide variety of applications including contro l, parameter adjustments, ac measurement and signal processing. features ? 128 resistor taps ? spi serial interface ? non-volatile storag e of wiper position ? wiper resistance: 70 typical @ 3.3v ? shutdown mode ? shutdown current 5a max ? power supply: 2.7v to 5.5v ?50k or 10k total resistance ? high reliability - endurance: 1,000,000 data c hanges per bit per register - register data retention: 50 years @ t +55 c ? 8 lead msop ? pb-free (rohs compliant) pinout isl22419 (8 ld msop) top view 1 2 3 4 8 7 6 5 sdo cs sdi v cc sck gnd shdn rw ordering information part number part marking resistance option (k ) temp. range (c) package (pb-free) pkg. dwg. # isl22419ufu8z* 419uz 50 -40 to +125 8 ld msop m8.118 ISL22419WFU8Z* 419wz 10 -40 to +125 8 ld msop m8.118 *add ?-tk? suffix for tape and reel. please refe r to tb347 for details on reel specifications. note: these intersil pb-free plastic packa ged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. data sheet september 8, 2009
2 fn6311.1 september 8, 2009 block diagram spi interface v cc gnd rw sck sdo sdi cs wr shdn power up interface , control and status logic non-volatile registers pin descriptions msop pin symbol description 1 sck spi interface clock input 2 sdo open drain data output of the spi serial interface 3 sdi data input of the spi serial interface 4cs chip select active low input 5 gnd device ground pin 6shdn shutdown active low input 7 rw ?wper? terminal of dcp 8v cc power supply pin isl22419
3 fn6311.1 september 8, 2009 absolute maximum rati ngs thermal information storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage at any digital interface pin with respect to gnd . . . . . . . . . . . . . . . . . . . . -0.3v to v cc +0.3 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v voltage at any dcp pin with respect to gnd . . . . . . . -0.3v to v cc i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma latchup (note 2) . . . . . . . . . . . . . . . . . . class ii, level b @+125c esd rating hbm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kv cdm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kv thermal resistance (typical, note 1) ja (c/w) 8 lead msop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 maximum junction temperature (pla stic package). . . . . . . .+150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions ambient temperature . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c v cc voltage for dcp operation . . . . . . . . . . . . . . . . . . 2.7v to 5.5v wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3ma to 3ma power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mw caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. jedec class ii pulse conditions and failure criterion used. level b exceptions are: us ing a max positive pulse of 6.5v on the shdn pin, and using a max negative pulse of -1v for all pins. analog specifications over recommended operating conditions unless otherwise stated. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temper ature limits established by characterization and are not production tested. symbol parameter test conditions min typ (note 3) max unit r total end-to-end resistance w option 10 k u option 50 k end-to-end resistance tolerance -20 +20 % end-to-end temperature coefficient w option 50 ppm/c (note 11) u option 80 ppm/c (note 11) r w (note 11) wiper resistance v cc = 3.3v @ +25c, wiper current = v cc /r total 70 c w (note 11) wiper capacitance 25 pf i lkgrw leakage on rw pin voltage at pin from gnd to v cc 24a voltage divider mode ( measured at r w , unloaded) inl (note 7) integral non-linearity -1 1 lsb (note 4) dnl (note 6) differential non-linearity monotonic over all tap positions -0.5 0.5 lsb (note 4) zserror (note 5) zero-scale error w option 0 1 5 lsb (note 4) u option 0 0.5 2 lsb (note 4) fserror (note 6) full-scale error w option -5 -1 0 lsb (note 4) u option -2 -1 0 lsb (note 4) tc v (notes 8, 11) ratiometric temperature coefficient dcp register set to 40 hex 4 ppm/c isl22419
4 fn6311.1 september 8, 2009 operating specifications over the recommended operating conditions unless otherwi se specified. parameters with min and/or max limits are 100% tested at +25c, unles s otherwise specified. temperature li mits established by characterization and are not production tested. symbol parameter test conditions min typ (note 3) max unit i cc1 v cc supply current (volatile write/read) 10k dcp, f spi = 5mhz; (for spi active, read and write states) 1ma v cc supply current (volatile write/read) 50k dcp, f spi = 5mhz; (for spi active, read and write states) 0.5 ma i cc2 v cc supply current ( non-volatile write/read) 10k dcp, f spi = 5mhz; (for spi active, read and write states) 3.2 ma v cc supply current ( non-volatile write/read) 50k dcp, f spi = 5mhz; (for spi active, read and write states) 2.7 ma i sb v cc current (standby) v cc = +5.5v, 10k dcp, spi interface in standby state 850 a v cc = +5.5v, 50k dcp, spi interface in standby state 160 a v cc = +3.6v, 10k dcp, spi interface in standby state 550 a v cc = +3.6v, 50k dcp, spi interface in standby state 100 a i sd v cc current (shutdown) v cc = +5.5v @ +85c, spi interface in standby state 3a v cc = +5.5v@ +125c, spi interface in standby state 5a v cc = +3.6v @ +85c, spi interface in standby state 2a v cc = +3.6v @ +125c, spi interface in standby state 4a i lkgdig leakage current, at pins shdn , sck, sdi, sdo and cs voltage at pin from gnd to v cc -1 1 a t wrt (note 11) wiper response time wiper response time after spi write to wr register 1.5 s t shdnrec (note 11) dcp recall time from shutdown mode from rising edge of shdn signal to wiper stored position and rh connection 1.5 s sck rising edge of last bit of acr data byte to wiper stored position and rh connection 1.5 s vpor power-on recall voltage minimum v cc at which memory recall occurs 2.0 2.6 v v cc ramp v cc ramp rate 0.2 v/ms t d power-up delay v cc above vpor, to dcp initial value register recall completed, and spi interface in standby state 3ms eeprom specification eeprom endurance 1,000,000 cycles eeprom retention temperature t +55 c 50 years t wc (note 9) non-volatile write cycle time from rising edge of cs 12 20 ms serial interface specifications v il shdn , sck, sdi, and cs input buffer low voltage -0.3 0.3*v cc v isl22419
5 fn6311.1 september 8, 2009 v ih shdn , sck, sdi, and cs input buffer high voltage 0.7*v cc v cc +0.3 v hysteresis shdn , sck, sdi, and cs input buffer hysteresis 0.05* v cc v v ol sdo output buffer low voltage i ol = 4ma 0 0.4 v r pu (note 10) sdo pull-up resistor off-chip maximum is determined by t ro and t fo with maximum bus load cbus = 30pf, f sck = 5mhz 2k cpin (note 11) shdn , sck, sdi, sdo and cs pin capacitance 10 pf f sck spi frequency 5mhz t cyc spi clock cycle time 200 ns t wh spi clock high time 100 ns t wl spi clock low time 100 ns t lead lead time 250 ns t lag lag time 250 ns t su sdi, sck and cs input setup time 50 ns t h sdi, sck and cs input hold time 50 ns t ri sdi, sck and cs input rise time 10 ns t fi sdi, sck and cs input fall time 10 20 ns t dis sdo output disable time 0 100 ns t v sdo output valid time 350 ns t ho sdo output hold time 0 ns t ro sdo output rise time r pu = 2k, cbus = 30pf 60 ns t fo sdo output fall time r pu = 2k, cbus = 30pf 60 ns t cs cs deselect time 2s notes: 3. typical values are for t a = +25c and 3.3v supply voltage. 4. lsb: [v(r w ) 127 ? v(r w ) 0 ] / 127. v(r w ) 127 and v(r w ) 0 are v(r w ) for the dcp register set to 7f hex and 00 hex respectively. lsb is the incremental voltage when changing from one tap to an adjacent tap. 5. zs error = v(rw) 0 / lsb. 6. dnl = [v(rw) i ? v(rw) i-1 ] / lsb-1, for i = 1 to 127. i is the dcp register setting. 7. inl = [v(rw) i ? (i ? lsb) ? v(rw) 0 ]/lsb for i = 1 to 127 8. for i = 16 to 127 decimal, t = -40c to +125c. max( ) is the maximum value of the wiper voltage and min ( ) is the minimum value of the wiper voltage over the temperature range. 9. t wc is the time from the end of a write sequence of spi serial in terface, to the end of the self-timed internal non-volatile write cycle. 10. r pu is specified for the highest data rate transfer for the dev ice. higher value pullup can be used at lower data rates. 11. this parameter is not 100% tested. operating specifications over the recommended operating conditions unless otherwi se specified. parameters with min and/or max limits are 100% tested at +25c, unles s otherwise specified. temperature li mits established by characterization and are not production tested. (continued) symbol parameter test conditions min typ (note 3) max unit tc v max v rw () i () min v rw () i () ? max v rw () i () min v rw () i () + [] 2 ? --------------------------------------------------------------------------------------------- - 10 6 165c ---------------- - = isl22419
6 fn6311.1 september 8, 2009 timing diagrams input timing output timing xdcp timing (for all load instructions) ... cs sck sdi sdo msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck sdo sdi addr msb lsb t dis t ho t v ... ... cs sck sdi msb lsb v w t wrt ... sdo high impedance t wc isl22419
7 fn6311.1 september 8, 2009 typical performance curves figure 1. wiper resistance vs tap position [ i(rw) = v cc /r total ] for 10k (w) figure 2. standby i cc vs v cc figure 3. dnl vs tap position in voltage divider mode for 10k (w) figure 4. inl vs tap position in voltage divider mode for 10k (w) figure 5. zs error vs temperature figure 6. zs error vs temperature 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 tap position (decimal) v cc = 3.3v, t = +125c v cc = 3.3v, t = +20c v cc = 3.3v, t = -40c wiper resisitance ( ) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.7 3.2 3.7 4.2 4.7 5.2 v cc (v) i sb (a) t = +25c t = +125c dnl (lsb) -0.2 -0.1 0 0.1 0.2 0 20 40 60 80 100 120 tap position (decimal) t = +25c v cc = 5.5v v cc = 2.7v -0.2 -0.1 0 0.1 0.2 0 20 40 60 80 100 120 tap position (decimal) inl (lsb) t = +25c v cc = 5.5v v cc = 2.7v -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 -40 -20 0 20 40 60 80 100 120 temperature (c) zs error (lsb) v cc = 5.5v v cc = 2.7v 50k 10k -1.5 -1.2 -0.9 -0.6 -0.3 0.0 -40 -20 0 20 40 60 80 100 120 temperature (oc) zs error (lsb) v cc = 5.5v v cc = 2.7v 50k 10k isl22419
8 fn6311.1 september 8, 2009 figure 7. end to end r total % change vs temperature figure 8. tc for voltage divider mode in ppm figure 9. midscale glitch, code 80h to 7fh figure 10. large signal settling time typical performance curves (continued) -1.0 -0.5 0.0 0.5 1.0 -40 -20 0 20 40 60 80 100 120 temperature (oc) end to end r total change (%) 0 15 30 45 60 75 90 105 16 36 56 76 96 tap position (decimal) tcv (ppm/c) 50k 10k signal at wiper (wiper unloaded) wiper mid point movement from 3fh to 40h signal at wiper (wiper unloaded movement from 7fh to 00h) scl isl22419
9 fn6311.1 september 8, 2009 pin description potentiometer pins rw rw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. the position of the wiper within the array is determined by the wr register. shdn the shdn pin forces the resistor to end-to-end open circuit condition and shorts rw to gnd. when shdn is returned to logic high, the previous latch settings put rw at the same resistance setting prior to shutdown. this pin is logically and with shdn bit in acr regi ster. spi interface is still available in shutdown mode and all registers are accessible. this pin must remain high for normal operation. bus interface pins serial clock (sck) this is the serial clock input of the spi serial interface. serial data output (sdo) the sdo is an open drain serial data output pin. during a read cycle, the data bits are shif ted out at the fa lling edge of the serial clock sck, while the cs input is low. sdo requires an external pull-up resistor for proper operation. serial data input (sdi) the sdi is the serial data input pin for the spi interface. it receives device address, operation code, wiper address and data from the spi external host device. the data bits are shifted in at the rising edge of the serial clock sck, while the cs input is low. chip select (cs ) cs low enables the isl22419, placing it in the active power mode. a high to low transition on cs is required prior to the start of any o peration after power up. when cs is high, the isl22419 is deselected and the sdo pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. principles of operation the isl22419 is an integrated circuit incorporating one dcp with its associated registers, non-volatile memory and the spi serial interface providing direct communication between host and potentiometer and memory. the resistor array is comprised of individual resistors connected in series. at either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. the electronic switches on the device operate in a ?make before break? mode when the wiper changes tap positions. when the device is powered down, the last value stored in ivr will be maintained in the non-volatile memory. when power is restored, the contents of the ivr is recalled and loaded into the wr to set the wiper to the initial value. dcp description the dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of each dcp are equivalent to the fi xed terminals of a mechanical potentiometer and internally connected to v cc and gnd. the rw pin of the dcp is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal within the dcp is controlled by an 7-bit volatile wiper register (wr). when the wr of a dcp contains all zeroes (wr[6:0]: 00h), its wiper terminal (rw) is closest to gnd. when the wr register of a dcp contains all ones (wr[6:0]: 7fh), its wiper terminal (rw) is closest to v cc . as the value of the wr increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to gnd to the closest to v cc . while the isl22419 is being powered up, the wr is reset to 40h (64 decimal), which locates rw roughly at the center between gnd and v cc . after the power supply voltage becomes large enough for reliable non-volatile memory reading, the wr will be reload with the value stored in a non-volatile initial value register (ivr). the wr and ivr can be read or written to directly using the spi serial interface as described in the following sections. memory description the isl22419 contains one non-volatile 7-bit register, known as the initial value register (ivr), volatile 7-bit wiper register (wr), and volatile 8-bit access control register (acr). the memory map of isl22419 is on table 1. the non-volatile register (ivr) at a ddress 0, contains initial wiper position and volatile register (wr) contains current wiper position. rw figure 11. dcp connection in shutdown mode table 1. memory map address non-volatile volatile 2? acr 1reserved 0ivr wr isl22419
10 fn6311.1 september 8, 2009 the non-volatile ivr and volatile wr registers are accessible with the same address. the access control register (acr) contains information and control bits described below in table 2. the vol bit (acr[7]) determines whether the access is to wiper registers wr or initial value registers ivr. if vol bit is 0, the non-volatile ivr register is accessible. if vol bit is 1, only the volatile wr is accessible. note, value is written to ivr register al so is written to the wr. the default value of this bit is 0. the shdn bit (acr[6]) disables or enables shutdown mode. this bit is logically and with shdn pin. when this bit is 0, dcp is in shutdown mode. default value of shdn bit is 1. the wip bit (acr[5]) is read on ly bit. it indicates that non- volatile write operation is in progress. the wip bit can be read repeatedly after a non-vola tile write to determine if the write has been completed. it is impossible to write to the wr or acr while wip bit is 1. shutdown mode the device can be put in shutdown mode either by pulling the shdn pin to gnd or setting the sh dn bit in the acr register to 0. the truth table for shutdown mode is in table 3. spi serial interface the isl22419 supports an spi serial protocol, mode 0. the device is accessed via the sdi input and sdo output with data clocked in on the rising edge of sck, and clocked out on the falling edge of sck. cs must be low during communication with the isl22419. sck and cs lines are controlled by the host or master. the isl22419 operates only as a slave device. all communication over the spi interface is conducted by sending the msb of each byte of data first. protocol conventions the first byte sent to the isl22419 from the spi host is the identification byte. a valid ident ification byte contains 0101 as the four msbs, with the fo llowing four bits set to 0. table 4. identification byte format the next byte sent to the isl22419 contains the instruction and register pointer informat ion. the four msbs are the instruction and two lsbs are register address (see table 5). table 5. identification byte format there are only two valid instruction sets: 1011(binary) - is a read operation 1100(binary) - is a write operation there are only two registers address possible for this dcp. if the r1, r0 bits are zero, then t he read or write is to either the ivr or the wr register (depends of vol bit at acr). if the r1 bit is 1and r0 bit is 0, then the operation is on the acr. write operation a write operation to the isl22419 is a three-byte operation. it requires first, the cs transition from high to low, then a valid identification byte, then a valid instruction byte followed by data byte is sent to sdi pi n. the host terminates the write operation by pulling the cs pin from low to high. for a write to address 0 (wr), th e byte at address 2 (acr[7]) determines if the data byte is to be written to volatile or both volatile and non-volatile registers. refer to ?memory description? on page 9 and figure 12. the internal non-volatile write cycle starts after rising edge of cs and takes up to 20ms. read operation a read operation to the isl22419 is a three byte operation. it requires first, the cs transition from high to low, then a valid identification byte, then a valid instruction byte followed by ?dummy? data byte is sent to sdi pin. the spi host reads the data from sdo pin on falling edge of sck. the host terminates the read operation by pulling the cs pin from low to high (see figure 13). in order to read back the non-volatile ivr, it is recommended that the application reads the a cr first to verify the wip bit is 0. if the wip bit (acr[5]) is not 0, the host should repeat its reading sequence again. table 2. access control register (acr) bit # 765 4321 0 bit name vol shdn wip 0000 0 table 3. shdn pin shdn bit mode high 1 normal operation low 1 shutdown high 0 shutdown low 0 shutdown 01010000 (msb) (lsb) 76543210 i3 i2 i1 i0 0 0 r1 r0 isl22419
11 fn6311.1 september 8, 2009 figure 12. three byte write sequence figure 13. three byte read sequence applications information communicating with isl22419 communication with isl22419 pr oceeds using spi interface through the acr (address 11b), ivr (address 00b) and wr (address 00b) registers. the wiper of the potentiometer is controlled by the wr register. writes and reads can be made directly to this register to control and monito r the wiper position without any non-volatile memory changes. this is done by setting msb bit (acr[7]) at address 11b to 1. the non-volatile ivr stores t he power up value of the wiper. ivr is accessible when msb bit (acr[7]) at address 11b is set to 0. writing a new value to the ivr register will set a new power up position for the wiper. also, writing to this register will load the same value into the wr as the ivr. reading from the ivr will not c hange the wr, if its contents are different. the typical application diagram is shown in figure 14. for proper operation adding 0.1f decoupling ceramic capacitor to v cc is recommended . the capacitor value may vary based on expected noise frequency of the design. 0 101 00 i3i2 i1i000 r1r0 sck sdi 0 d6 d5d4 d3 d2 d1d0 cs 00 0 0 101 00 i3 i2 i1 i0 0 0 r1 r0 sck sdi cs 00 sdo 0 d6 d5d4 d3 d2 d1d0 don?t care 0 isl22419
12 fn6311.1 september 8, 2009 examples: a . writing to the ivr: this sequence will write a new value (77h) to the ivr(non-volatile): set the acr (addr 02h) for nv write (40h) send the id byte, instruction byte, then the data byte 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 (sent to sdi) set the ivr (addr 00h) to 77h send the id byte, instruction byte, then the data byte 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1 (sent to sdi) b. reading from the wr: this sequence will read the value from the wr (volatile): write to acr first to access the wr send the id byte, instructio n byte, then the data byte 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 (sent to sdi) read the data from wr (addr 00h) send the id byte, instruction byte, then read the data byte 0 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 x x x x x x x x (out on sdo) v cc v cc v cc r1 r2 0.1f isl22419 cs sdo rw 0.1f shdn rpu v out figure 14. typical application diagram for implementing adjustable voltage referance sdi sck isl22419
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6311.1 september 8, 2009 isl22419 mini small outline plastic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only. l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m8.118 (jedec mo-187aa) 8 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.026 bsc 0.65 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n8 87 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 05 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 2 01/03

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